1. Field of the Invention
The present invention relates to a non-volatile memory device. More particularly, the invention relates to a non-volatile memory device capable of generating a program voltage in accordance with a number of program/erase operations applied to memory cells in the device.
2. Description of the Related Art
An electrically erasable/programmable non-volatile memory device is capable of retaining data even when supply of power is discontinued. A flash memory is a representative example of electrically erasable/programmable non-volatile memory device.
In particular, a NAND-type flash memory has a string construction in which a plurality of flash memory cells are connected in series, and thus can easily be integrated and may be fabricated at low cost. For this reason, the NAND-type flash memory has been used as data memory for various types of portable products.
A memory cell within a flash memory is programmed or erased using a physical phenomenon known as F-N tunneling. Certain general principals associated with the programming or erasing of a memory cell in a flash memory will now be described.
During an erasing operation, a ground voltage is applied to the control gate of a memory cell transistor, and a high voltage (i.e., a voltage greater than a nominally supply voltage) is applied to the semiconductor substrate (or bulk) associated with the memory cell. Under these erasure bias conditions, a strong electric field is formed between a floating gate and the bulk. Due to the large difference between voltages apparent at the floating gate and bulk, electrons accumulated on the floating gate are discharged to the bulk by F-N tunneling. In other words, a threshold voltage for the erased cell transistor is moved in a negative direction.
During a programming operation for the memory cell, a high voltage (i.e., a voltage greater than the supply voltage) is applied to the control gate of the constituent cell transistor, and a ground voltage is applied to the drain of the cell transistor and the bulk. Under these bias conditions, electrons are injected onto the floating gate of the cell transistor by F-N tunneling. In other words, a threshold voltage for the programmed cell transistor is moved in a positive direction.
FIG. 1 is a block diagram of a NAND-type flash memory device 100 presented as an example of a non-volatile memory device. The NAND-type flash memory device 100 generally includes a memory cell array 110, a row decoder 130, and a page buffer circuit 150.
The memory cell array 110 is divided into a plurality of memory blocks (not shown), each including a plurality of strings 110_1 through 110_M that extend in a row direction. FIG. 1 illustrates only one memory block for convenience of explanation.
Each of the strings 110_1 through 110_M includes a string selecting transistor SST, a ground selecting transistor GST, and a plurality of memory cell transistors MCT<0> through MCT<N−1> connected in series between the string selecting transistor SST and the ground selecting transistor GST.
The gate of the string selecting transistor SST is connected to a string selection line SSL, and the drain of the string selecting transistor SST is connected to a corresponding bit line BLe or BLo. The gate of the ground selecting transistor GST is connected to a ground selection line GSL, and the source is connected to a common source line CSL. The control gate of each of the memory cell transistors MCT<0> through MCT<N−1> is connected to a corresponding word line of word lines WL<0> through WL<N−1>.
Here, the voltage applied to each of the lines SSL, WL<0> through WL<N>, and GSL is controlled by the row decoder 130 in response to a predetermined timing control signal (not shown), and the voltage apparent on each pair of adjacent bit lines BLe and BLo is controlled by a page buffer (not shown) in the page buffer circuit 150.
A conventional method well know to those skilled in the art may be used to control the lines SSL, WL0 through WLn, and GSL and the pairs of the bit lines BLe and BLo. Hence, a more detailed description will be omitted for the sake of brevity.
In general, an incremental step pulse programming (ISPP) method is used to program respective cell transistors. In the ISPP method, a memory cell is repeatedly programmed while gradually increasing the program voltage, thereby precisely controlling a distribution of threshold voltages for the memory cell.
FIG. 2 is an exemplary timing diagram for a program voltage VPGM applied to a non-volatile memory device within the operation of a conventional ISPP method. As illustrated in FIG. 2, the program voltage VPGM is gradually increased by a step voltage VSTEP, starting from a starting voltage VSTART.
The more programming and/or erasing operations are repeatedly performed in a non-volatile memory device, the shorter the program time required for programming. The program time is shortened mainly due to a well understood charge trapping effect. “Charge trapping” refers to a phenomenon in which some of electrons injected onto a floating gate are captured during programming operations by the oxide layer that exists between the floating gate and a bulk. Thus, the more program/erase operations are performed, the greater the charge trapping effects become.
More particularly, charge trapping effects are associated with the cell transistor on a non-volatile memory cell. As the quantity of trapped charge apparent in the oxide layer increases, fewer electrons must be injected to program the cell transistor. As a result, programming time is reduced.
This effect notwithstanding, a like programming voltage (see, FIG. 2) is applied to cell transistors of a non-volatile memory, regardless of programming time variations associated with charge trapping effects. As a result, the program stress caused by application of the program voltage to the cell transistor is unnecessarily increased. As is well understood by those skilled in the art, over-programming results from program stress. Over-programming results in an undesired migration of threshold voltage for the cell transistor, and prevents data stored in the cell transistor from being accurately read.
Also, when program/erase operations are repeatedly performed in relation to one cell transistor of a non-volatile memory device, charge trapping may occur in all cell transistors associated with the non-volatile memory device, thereby lowering the reliability of the device. Accordingly, there is a need to develop a programming method providing improved reliability for non-volatile memory devices even when program/erase operations are repeatedly performed.